A field-emission cathode (or field emitter) contains a group of electron-emissive elements that emit electrons upon being subjected to an electric field of sufficient strength. The electron-emissive elements are typically situated over a patterned layer of emitter electrodes. In a gated field emitter, a patterned gate layer typically overlies the patterned emitter layer at the locations of the electron-emissive elements. Each electron-emissive element is exposed through an opening in the gate layer. When a suitable voltage is applied between a selected portion of the gate layer and a selected portion of the emitter layer, the gate layer extracts electrons from the electron-emissive elements at the intersection of the two selected portions.
The electron-emissive elements are often shaped as cones. Referring to the drawings, FIGS. 1a-1d illustrate a conventional technique as, for example, disclosed in Spindt et al, U.S. Pat. No. 3,755,704, for creating conical electron-emissive elements in a gated field emitter for a flat-panel CRT display. At the stage shown in FIG. 1a, the partially finished field emitter consists of an electrically insulating substrate 20, an emitter electrode layer 22, an intermediate dielectric layer 24, and a gate layer 26. Gate openings 28 extend through gate layer 26. Corresponding, somewhat wider dielectric openings 30 extend through dielectric layer 24.
Using a grazing-angle deposition procedure, a lift-off layer 32 is formed on top of gate layer 26 as depicted in FIG. 1b. Emitter material is deposited on top of the structure and into dielectric openings 30 in such a way that the apertures through which the emitter material enters openings 30 progressively close. In U.S. Pat. No. 3,755,704, a closure material is simultaneously deposited at a grazing angle to help close the deposition apertures. Generally conical electron-emissive elements 34A are thereby formed in composite openings 28/30 over emitter layer 22. See FIG. 1c. A continuous layer 34B of the emitter/closure material forms on top of gate layer 26. Lift-off layer 32 is subsequently removed with a suitable etchant to lift off (i.e., remove) excess emitter/closure-material layer 34B. FIG. 1d shows the resultant structure.
Removing lift-off layer 32 in order to lift off excess emitter/closure-material layer 34B is typically adequate when (a) the topography of the structure below lift-off layer 32 is smooth and (b) excess emitter/closure-material layer 34B is porous so that the lift-off etchant can readily penetrate excess layer 34B to attack lift-off layer 32. However, gate layer 26 is usually a patterned layer consisting of multiple laterally separated portions that cause significant roughness in the topography of the structure below lift-off layer 32. Parts of layer 32 sometimes remain in the spaces between the portions of gate layer 26, especially when the gate portions are close together.
Also, due to the surface roughness, the initial thickness of lift-off layer 32 is non-uniform. In particular, the non-uniformity is frequently so great that portions of the lift-off material do not initially accumulate at certain areas in the spaces between the gate portions. Portions of excess layer 34B are directly attached to gate layer 26 and/or dielectric layer 24 at these areas, and are therefore not lifted off during the removal of lift-off layer 32. The net result is that pieces of excess layer 34B often remain in the spaces between the gate portions. This can lead to short circuiting between the portions of gate layer 26.
If excess emitter/closure-material layer 34B is not porous, the etchant can access lift-off layer 32 only through pin holes and at the edges of the structure. The etch time often becomes excessively long. It is desirable to remove excess layer 34B rapidly and in a way that avoids short circuiting concerns.